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? idt and the idt logo are registered trademar ks of integrated device technology, inc. ? 201 1 integrated device technology, inc 1 february 8, 2011 device overview the idt 89HP0504PB (p0504pb) is a 5gbps pcie? repeater device featuring idt eyeboost? techno logy that compensates for cable and board trace attenuations and isi ji tter, thereby extending connection reach. the device is optimized for pcie gen1 and gen2 high speed serial data streams and contains four data channels, each able to process 5gbps transmission rates. each channel consists of an input equalizer and amplifier, signal detection with glitch filter, as well as programmable output swing and de- emphasis. allowing for application specific optimization, the p0504pb, with its configurable receiver and transmitter features, is ideal fo r pcie applications using a wide combination of cables and board trace materials. all modes of active data transfer are designed with minimized power consumption. in full shutdown mode, the part consumes less than 40mw in worst case environmental conditions. applications ? blade servers, rack servers ? pcie instrumentation ? storage systems ? cabled pcie devices features ? compensates for cable and pc b trace attenuation and isi jitter ? programmable receiver equalization up to 24db ? programmable transmitte r swing and de-emphasis ? recovers data stream even when the differential signal eye is completely closed due to trace attenuation and isi jitter ? full pcie protocol support ? configurable via external pins ? leading edge power minimization in active and shutdown modes ? no external bias resistors or reference clocks required ? channel mux mode, demux mode, 1 to 2 channels multicast, and z-switch function mode ? available in a 36-pin qfn package (4.0 x 7.5mm with 0.5mm pitch) benefits ? extends maximum cable length to over 8 meters and trace length over 48 inches in pcie applications ? minimizes ber 89HP0504PB data sheet 4 channel 5gbps pcie? signal repeater typical application figure 1 idt repeaters in blade servers (trace) server pcie gen1,2 idt repeater pcie gen1,2 (trace, eg. fr4) server chipset pcie gen1,2 (trace, eg. fr4) chipset idt repeater backplane
idt 89HP0504PB data sheet 2 february 8, 2011 pcie compliance the device was designed to provide end us ers with features needed to comply with pcie system application requirements: ? receiver detection support, pcie beacon support ? receiver supports high impedance mode for pcie ? jitter, eye opening, and all other key ac and dc specifications. block diagram the p0504pb contains four hi gh speed channels as shown in figure 2 . each channel can be routed to different outputs. depending on user configuration via mode selections, input tra ffic can be muxed or demuxed. powerdown (p db) and receiver detection reset (rstb) a re provided for state and channel control. figure 2 block diagram
3 february 8, 2011 device overview ................................................................................................................ ................ 1 applications................................................................................................................... ..................... 1 features....................................................................................................................... ...................... 1 benefits ....................................................................................................................... ....................... 1 typical application ............................................................................................................ ................. 1 pcie compliance ................................................................................................................ ............... 2 block diagram.................................................................................................................. .................. 2 functional description ......................................................................................................... .............. 5 power-up....................................................................................................................... ............ 6 power sequencing............................................................................................................... ...... 6 idt eyeboost? technology ..................................................................................................... 6 eye diagram parameters ......................................................................................................... .7 receiver impedance............................................................................................................. ..... 7 transmitter impedance.......................................................................................................... .... 7 pcie receiver detection support.............................................................................................. 8 modes of operation ............................................................................................................. ...... 8 channel muxing................................................................................................................. ........ 9 electrical specifications ...................................................................................................... ............. 13 absolute maximum ratings ..................................................................................................... 13 recommended operating conditions...................................................................................... 13 power consumption .............................................................................................................. .. 14 package thermal considerations............................................................................................ 14 dc specifications .............................................................................................................. ...... 15 ac specifications.............................................................................................................. ....... 15 pin description................................................................................................................ ................. 20 package pinout ? 36-qfn signal pinout ....................................................................................... 22 pin diagram .................................................................................................................... ................. 23 qfn package dimension .......................................................................................................... ...... 24 revision history ............................................................................................................... ................ 25 ordering information........................................................................................................... ............. 26 table of contents
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idt 89HP0504PB data sheet 5 february 8, 2011 functional description the p0504pb has 4 channels, each with the indi vidually programmable features listed below. figure 3 diagrams the channel and table 1 summarizes key configuration options. figure 3 channel block diagram with channel features ? per-channel programmable featur es used at the receive side. ? input equalization with 3 levels: 2 to 14db compensation fo r high frequency signal attenuation due to cables and board traces. additionally, up to 10db boost is added automatically by the equalizer for applic ations using long cables. the total equalization range is be tween 2db and 24db. ? input high impedance control via channel enable: di sabled (active mode) and hi-z (power-down). ? per-channel programmable featur es used at the transmit side. ? output de-emphasis with 8 levels: 0 to -6 .5db. the de-emphasis boosts the magnitude of higher frequencies sent by the transmitt er to compensate for high frequency losses travelli ng through output side cable or output side board traces. this ensures that the fi nal received signal has a wider eye opening. ? output differential swing with 3 le vels: 0.5v to 0.95v (peak-to-peak). ? receiver detection: enable or disable. this function is activated following an rstb pulse. ? with receiver detection enabled, if a0 and a1 channels do not detec t at least one receiver, then the p0504pb on-chip rx termina tion on a0 and a1 is set to hi-z as shown in table 2 . ? with receiver detection enabled, if b0 and b1 channels do not detec t at least one receiver, then the p0504pb on-chip rx termina tion on b0 and b1 is set to hi-z as shown in table 2 . ? electrical idle detection: when the incoming differential peak- peak amplitude falls below 110mv, the device enters electrical i dle mode and the corresponding transmitter stops toggling, maintains its comm on mode voltage level, and meets all electrical idle specificat ions described in the ac specifications section of this data sheet. in addition, the device contains gl obal configuration of the data path: ? transfer modes: direct connec t, cross-connect, multicast. input termination [ 100 ohm [ electrical idle detection with glitch filter programmable equalizer 0 to 14db up to 10db auto-boost programmable transmitter [ de-emphasis: 0 to -6.5db [ voltage swing: 500mv to 950mv channel power-down + _ output termination [ 100 ohm [ receiver detection + _
idt 89HP0504PB data sheet 6 february 8, 2011 power-up after the power supplies reach their minimu m required levels, the p0504pb powers up by setting all input and output pins to kno wn states: ? all the device's input configuration pins ar e set internally to vss or vdd for 2-le vel pins and to vdd/2 for 3-level pins. ? high speed differential input and output pins depend on various conditions described below: ? high speed differential input and output pins are in hi gh impedance if any of the following conditions is true: ? powerdown is set (pdb pin = 0v) or ? no receiver termination was detected at tx outputs in all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impeda nce. also refer to table 4 , power reducing modes , table 2 , receiver impedance , and table 3 , transmitter impedance . the power ramp up time for the p0504pb should be less than 1ms. power sequencing there are no power sequencing c onstraints for the p0504pb. idt eyeboost? technology idt eyeboost? technology is a method of data stream recovery even when the di fferential signal eye is complete ly closed due to cable or trace attenuation and isi jitter. with idt eyeboost?, the system desi gner can both recover the incoming data and retransmit it to tar get device with a maximized eye width and amplitude. an example of idt eyeboost? technology usage in a system application and eye diagram results are shown in figure 4 . in this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch fr4 connection from signal sour ce and the (b) diagram shows differential signal at the output of repeater maximized eye opening with idt eyeboost? technology. figure 4 eye diagram (a) (b)
idt 89HP0504PB data sheet 7 february 8, 2011 eye diagram parameters receiver impedance the table below shows how the receiver impedan ce changes based on input and output pin states. transmitter impedance the table below shows how the transmitter impedance changes based on input and output pin states. feature feature type parameter names for programming via pins input equalization main eye optimization a0rxeq, a1rxeq, b0rxeq, b1rxeq range: 0db to 14db (plus additional auto- boost up to 10db for long connections) output differential signal swing (peak-to-peak) and output de-emphasis main eye optimization a0txsw, a1txsw, b0txsw, b1txsw range: 0.5v to 0.95v for swing range: 0 to -6.5db for de-emphasis table 1 quick reference: parame ters used for eye optimization mode control inputs rx terminations description pdb [a,b]rxdeten rstb full ic power-down 0 x x hi-z receiver terminations placed in hi-z. channel enabled 1 0 1 50 receiver detect disabled. receiver terminations set to 50 . channel enabled 1 1 1 50 receiver detect enabled. valid receiver detected. receiver terminations set to 50 . mode control inputs tx termina- tions description [a,b]rxdeten rstb full ic power-down x x 1k receiver terminations placed in hi-z. channel enabled 0 1 50 rx signal not detected. receiver detect disabled. receiver terminations set to hi-z. table 3 transmitter impedance (part 1 of 2)
idt 89HP0504PB data sheet 8 february 8, 2011 pcie receiver detection support the p0504pb transmitter fully supports pcie receiver detecti on requirements. receiver detec tion is enabled for channels a0 and a1 by asserting pin arxdeten and for channels b0 and b1 by as serting pin brxdeten. for receiver detecti on to occur, a low pulse (minimum 200ns) must be applied at pin rstb. the rising edge of the rs tb signal starts the receiver detection pr ocedure. neither arxdeten nor brxdeten can be toggled during the receiver detection procedure, i.e ., they must be kept high for at least 200ns before the rstb rising edge and they c annot go to low sooner than 2ms from the time the rstb goes high. the receiver detection takes place once per rstb pulse. figure 5 receiver detection timing modes of operation the device supports several data transfer modes, electr ical idle mode, and several power reducing modes. electrical idle mode in electrical idle mode, the transmitter stops toggling and maintains its common-mo de voltage level. the device enters electric al idle mode when the envelope of the incoming signal on a given channel has fallen below a programmable threshold level. power reducing modes the repeater supports five power-down st ates and one active state as shown in table 4 . the user can choose between full chip power-down, channel based power-down, and electrical idle modes. po wer reducing modes can be selected via pdb and rstb. channel enabled 0 1 50 rx signal detected. receiver detect disabled. receiver terminations set to 50 . channel enabled but inactive 1 1 50 tx output is squelched. a valid receiver was detected. receiver terminations set to 50 . output common-mode is held at its active value. channel enabled and active 1 1 50 tx output is active. a valid receiver was detected. receiver terminations set to 50 . mode control inputs tx termina- tions description [a,b]rxdeten rstb table 3 transmitter impedance (part 2 of 2) rstb t2 = 1.5us vc m vdd rxdetstat (i t l) t1 = 800us t0 >= 200 ns t3 >0ns t4 >= 2ms rxdeten rstb t2 = 1.5us vc m vdd rstb t2 = 1.5us vc m vdd rxdetstat (i t l) t1 = 800us t0 >= 200 ns t3 >0ns t4 >= 2ms rxdeten
idt 89HP0504PB data sheet 9 february 8, 2011 channel muxing the p0504pb repeater permits a variety of mu xing, demuxing, and switching configurations, and it can mux/de-mux 1 or 2 bi-direc tional pcie lanes (4 pcie channels) into 2 target devic es. these configurations require the sele ction of specific pins for input and output ports. in the following sections, each configuration is described in terms of pin connectivity to exte rnal upstream and downstrea m devices. the configu rations shown are those often used in system designs: ? uni-directional 2:1 mux (1 or 2 instances) ? uni-directional 1:2 de-mux (1 or 2 instances) ? bi-directional 2:1 mux/de-mux ? bi-directional z-function (also called partial cross function) the p0504pb supports channel muxing in both upstream and downstream channel directions via the chsel pin, as shown below. figure 6 shows the channel/reference muxing modes and table 5 shows how chsel (channel transfer selection) pi n allows for various modes of data transfers: multicast mode, direct-connect, and cross- connect. both direct-connect, and cross-connec t modes are used to build uni-direction al and bi-directional 2:1 mux and z-switch functions. power reducing mode required signal values state description power- down control receiver detect start pdb rstb full ic power-down 0 x all channels are powered-down receiver detect reset rx termination is set to hi-z tx termination is set to 1k tx common-mode is at vdd receiver detect reset 1 0 receiver detect state machine receiver terminations placed in hi-z tx termination is set to 1k tx common-mode is at vdd channel enabled but inactive (electrical idle). rx and tx set to hi-z 1 1 tx output is squelched no receiver was detected receiver terminations placed in hi-z tx termination is set to 1k tx common-mode is at vdd channel enabled but inactive (electrical idle). rx and tx set to 50 ohms 1 1 tx output is squelched a valid receiver was detected receiver terminations set to 50 output common-mode is held at its active value tx termination is set to 50 channel enabled and active. no power-down 1 1 tx output is active a valid receiver was detected receiver terminations set to 50 transmitter terminations set to 50 table 4 power reducing modes
idt 89HP0504PB data sheet 10 february 8, 2011 figure 6 diagram of channel/reference muxing modes uni-directional 2:1 mux or two instances of unidirectional 2:1 mux this function can be achieved by using the chsel pin as a mux control signal. chsel s hould be set to either vdd or open. the po rts should be configured as shown in figure 7 . input pins output pins chsel a0rx[p,n] a1rx[p,n] b0rx[p,n] b1rx[p,n] a0tx[p,n] a1tx[p,n] b0tx[p,n] b1tx[p,n] chsel=vss (multicast mode) a0 data x b0 data x a0 data a0 data b0 data b0 data chsel=open (direct-connect mode) a0 data a1 data b0 data b1 data a0 data a1 data b0 data b1 data chsel=vdd (cross-connect mode) a0 data x b0 data x squelched a0 data squelched b0 data table 5 description of cha nnel muxing/de-muxing functionality
idt 89HP0504PB data sheet 11 february 8, 2011 figure 7 implementation of unidirectional 2:1 mux as an alternative, different chip channels can also be selected as shown in figure 8 . this solution can be combined with the previous one to obtain two instances of uni-directional 2:1 mux. figure 8 implementation of second in stance of unidirectional 2:1 mux uni-directional 1:2 de-mux or two instances of unidirectional 1:2 de-mux this function can be achieved by using chsel pin as a de-mux c ontrol signal. chsel should be set to either vdd or open. the por ts should be configured as shown in figure 9 . figure 9 implementation of unidirectional 1:2 de-mux as an alternative, different chip c hannels can also be selected as shown in figure 10 . this solution can be combined with the previous one to obtain two instances of uni-directional 1:2 de-mux. a0rx(p,n) a1rx(p,n) a1tx(p,n) device #1 device #2 device #3 chsel chsel = vdd: out = a chsel = open: out = b out a b b0rx(p,n) b1rx(p,n) b1tx(p,n) device #1 or #4 device #2 or #5 device #3 or #6 chsel chsel = vdd: out = a chsel = open: out = b out a b a0tx(p,n) a1tx(p,n) a0rx(p,n) device #2 device #3 device #1 chsel chsel = open: a = in chsel = vdd: b = in in a b
idt 89HP0504PB data sheet 12 february 8, 2011 figure 10 implementation of second instance of unidirectional 1:2 de-mux bi-directional 2:1 mux/de-mux the bi-directional mux and de-mux function c an also be achieved by using the chsel pi n as a mux control signal. chsel should be set to either vdd or open. the ports shoul d be configured as shown in figure 11 . figure 11 implementation of bi--directional 2:1 mux/de-mux bi-directional z-function (also called partial cross function) this function can also be achieved by using the chsel pin as a flow control signal. ch sel should be set to either vdd or open. the ports should be configured as shown in figure 12 . figure 12 implementation of z-function b0tx(p,n) b1tx(p,n) b0rx(p,n) device #2 or #5 device #3 or #6 device #1 or #4 in a b chsel chsel = open: a = in chsel = vdd: b = in device #1 device #2 device #3 chsel chsel = vdd: i/o = a chsel = open: i/o = b i/o a b a0rx(p,n) b1tx(p,n) a1rx(p,n) b0tx(p,n) a1tx(p,n) b0rx(p,n) device #1 device #2 device #3 device #4 a0tx(p,n) b1rx(p,n) a1tx(p,n) b0rx(p,n) a0rx(p,n) b1tx(p,n) a1rx(p,n) b0tx(p,n) chsel=open chsel=open c h s e l = v d d
idt 89HP0504PB data sheet 13 february 8, 2011 electrical specifications absolute maximum ratings note: all voltage values, except differential voltages , are measured with respect to ground pins. warning: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the devic e. these are stress ratings only and functional operation of the device at these or any conditions beyond thos e indicated under recommended operating condi tions is not implied. exposure to absolute-maxi mum-rated conditions for extended peri ods may affect device reliability. recommended operating conditions parameter value unit supply voltage range vdd ?0.5 to 1.35 v voltage range differential i/o ?0.5 to vdd +0.5 v control i/o ?0.5 to vdd + 0.5 v esd requirements: electrostatic discharge human body model 2000 v esd requirements: charged-device model (cdm) 500 v esd requirements: machine model 125 v storage ambient temperature -55 to 150 c table 6 absolute maximum ratings parameter notes min typical max unit power supply pin requirements vdd 1.2v dc analog supply voltage (specified at bump pins) 1.14 1.2 1.26 v temperature requirements ta ambient operating temperature - commercial 0 ? 70 c ambient operating temperature - industrial -40 ? 85 c tjunction junction operating temperature 0 ? 125 c table 7 operating conditions
idt 89HP0504PB data sheet 14 february 8, 2011 power consumption table 8 below lists power consumption values under typical and maximum operating conditions. package thermal considerations the data in table 9 below contains information that is relevant to the thermal per formance of the 36-pin qfn package. note: it is important for the reliability of this device in any user environment that the juncti on temperature not exceed the t j(max) value specified in table 9 . consequently, the effective junction to ambient thermal resistance ( ja ) for the worst case scenario must be maintained below the value deter mined by the formula: ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ja becomes a known entity to the system designer. how to achieve the desired ja is left up to the board or system designer, but in general, it can be achieved by adding the effects of jc (value provided in table 9 ), thermal resistance of the chosen adhesive ( cs ), that of the heat sink ( sa ), amount of airflow, and properties of the circuit board (number of laye rs and size of the board). parameter notes min typical max unit active mode i vdd current into vdd supply ? 330 500 ma p d full chip power 1 1. maximum power under all conditions. power is reduced by sele cting smaller de-emphasis settings (closer or equal to 0db). 400 600 mw p d-ch power per channel 1 100 150 mw standby mode full chip standby 30 40 mw table 8 power consumption parameter description value conditions units t j(max) junction temperature 125 maximum o c t a(max) ambient temperature 70 maximum for commercial-rated products o c 85 maximum for industrial-rated products o c ja(effective) effective thermal resistance, junction-to-ambient 41.8 zero air flow o c/w 36.1 1 m/s air flow o c/w 35.3 2 m/s air flow o c/w 34.3 3 m/s air flow o c/w 33.7 4 m/s air flow o c/w 33.2 5 m/s air flow o c/w jb thermal resistance, junction-to-board 14.5 na o c/w jc thermal resistance, junction-to-case 37.2 na o c/w table 9 thermal specifications for p0504pb, 4.0x7.5mm 36-qfn package
idt 89HP0504PB data sheet 15 february 8, 2011 dc specifications ac specifications latency specification parameter description min typ max unit v il digital input signal voltage low level 1 1. applies to all input pins. -0.3 ? 0.25*vdd-0.1 v v im digital input signal voltage mid level 2 2. applies to all 3-level input pins. 0.25*vdd+ 0.1 0.75*vdd-0.1 v v ih digital input signal voltage high level 1 0.75*vdd+ 0.1 vdd+ 0.3 v v hys hysteresis of schmitt trigger input 0.1 ? v i il input current 3 3. applies only to 2-level i nput pins with default values set to vdd in the pin description table ( table 14 ). ? 100 a i ih input current 4 4. applies only to 2-level i nput pins with default values set to vss in the pin de scription table ( table 14 ). ? 100 a i il1 input current 2 ? 180 a i ih1 input current 2 ? 180 a r weak_pd_2l internal weak pull-down resistor at 2-level input pads 4 11 ? k ohm r weak_pu_2l internal weak pull-up resistor at 2-level input pads 3 11 ? k ohm r weak_pd_3l internal weak pull-down resistor at all 3-level input pads 6.3 ? k ohm r weak_pu_3l internal weak pull-up resistor at all 3-level input pads 6.3 ? k ohm table 10 dc specification parameter description min typical max unit latency input to output signal propagation device ? 300 ? ps table 11 latency specification
idt 89HP0504PB data sheet 16 february 8, 2011 receiver specifications parameter description min typical max unit receiver input jitter specifications t rx-ddj receive input signal data dependent jitter (inter-sym - bol interference). ? ? >1 ui t rx-tj receive input signal total jitter ? ? >1 ui t rx-eye receiver eye time opening (can recover from closed eye due to trace attenuation and isi jitter) 0 ? ? ui receiver input eye specification v rx-diff-pp-dc receiver differential peak-peak voltage 1 1. the minimum value of 0 mv represents the case when eye is completely closed. 0 ? 2000 mv v rx-cm-dc receiver dc common mode voltage ? 0 ? mv v rx-cm-ac-p receiver ac common mode voltage ? ? 150 mv receiver return loss rl rx-diff-f1 receiver differential return loss (0 - 1.25ghz) ? ? -10 db rl rx-diff-f2 receiver differential return loss (1.25 - 2.5ghz) ? ? -8 db rl rx-cm receiver common-mode dc return loss ? ? -6 db receiver dc impedance z rx-dc receive impedance (singled-ended) 40 50 60 ohm z rx-diff-dc dc differential impedance 80 100 120 ohm z rx-high-imp-dc-pos dc input common-mode receive high impedance for input voltage from 0v to 200mv 50k ? ? ohm z rx-high-imp-dc-neg dc input common-mode receive high impedance for input voltage from 0v to -200mv 1k ? ? ohm z diff-hiz-pos differential receive high impedance for input voltage from 0v to 200mv 200k ? ? ohm z diff-hiz-neg differential receive high impedance for input voltage from 0v to -200mv 4k ? ? ohm receiver signal detection v rx-idle-det-diffp-p electrical idle signal detect threshold 70 110 150 mv t rx-idle-det-diff-enter - time unexpected electrical idle enter detect threshold inte - gration time ? ? 10 ms t sigdet-attack signal detect valid signal attack time (turn-on time) ? ? 15 ns t sigdet-decay signal detect valid signal decay time (turn-off time) ? ? 15 ns t sigdet-att-decay-mis signal detect attack / decay time mismatch ? ? 5 ns table 12 receiver electrical specifications
idt 89HP0504PB data sheet 17 february 8, 2011 transmitter specifications parameter description min typical max unit output eye and common voltage specification v tx-diff-pp differential transmitter swing [a:b]xtxsw=1 [a:b]xtxsw=open 800 700 950 800 1100 950 mv v tx-diff-pp-low low power differential p-p transmitter swing [a:b]xtxsw=0 400 500 650 mv d tx-deemp output de-emphasis. defined as 20log(v tx-de-emp / v tx- diff ) [db] -6.5 ? 0 db v tx-de-ratio-3.5db tx de-emphasis level ratio [a:b]xtxsw=open -4.0 ? -3.0 db v tx-de-ratio-6db tx de-emphasis level [a:b]xtxsw=1 -6.5 ? -5.5 db t tx-rise-fall rise/fall time 0.125 ? ? ui t rf-mismatch tx rise/fall mismatch ? ? 0.1 ui t res-dj-5gbps-1 residual deterministic jitter at output pins (1 inch fr4 trace before receiver input pins, 5gbps) 1 ? ? <0.1 ui t res-dj-5gbps-2 residual deterministic jitter at output pins (40 inch fr4 trace before receiver input pins, 5gbps 1 ? 0.15 0.2 ui v tx-cm-ac-pp pk-pk ac common mode voltage variation ? ? 50 mv v tx-cm-ac-p tx ac common mode voltage (2.5 gt/s) ? ? 20 mv v tx-cm-rms-ac rms ac common mode voltage variation ? ? 20 mv v tx-dc-cm transmitter dc common-mode voltage 0 ? vdd v v tx-cm-dc-linedelta absolute delta of dc common mode voltage between p and n 0 ? 25 mv c tx ac coupling capacitor 75 ? 200 nf transmitter dc impedance z tx-diff-dc transmitter output differential dc impedance 2 80 100 120 ohm i tx-short transmitter short-circuit current limit ? ? 90 ma transmitter return loss rl tx-diff-f1 transmitter differential return loss (0 - 1.25ghz) ? ? -10 db rl tx-diff-f2 transmitter differential return loss (1.25 - 2.5ghz) ? ? -8 db rl tx-cm transmitter common-mode dc return loss ? ? -6 db electrical idle v tx-idle idle output voltage ? ? 20 mv v cm-delta-squelch maximum common-mode step entering/exiting electrical idle mode ? ? 50 mv table 13 transmitter electrical requirements (part 1 of 2)
idt 89HP0504PB data sheet 18 february 8, 2011 figure 13 residual jitter characterization test setup v tx-cm-dc-activeidle- delta absolute delta of dc common mode voltage during l0 and electrical idle. 0 ? 100 mv v tx-idle-diff-ac-p electrical idle differential peak output voltage 0 ? 20 mv v tx-idle-diff-dc dc electrical idle differential output voltage 0 ? 5 mv lane skew l tx-skew lane-to-lane output skew ? 5 10 ps receiver detect v tx-rcv-detect voltage change allowed during receiver detection ? ? 600 mv t0 rstb negative pulse width 200 ? ? ns t1 vcm pulsing (ramp up) ? 800 ? s t2 vcm pulsing (ramp down) ? 1.5 ? s t3 time from rxdeten high to rstb pulse 0 ? ? ns 1. refer to figure 13 . 2. when term_ctl bit is set to 100 . parameter description min typical max unit table 13 transmitter electrical requirements (part 2 of 2) a ? fr4 trace b ? sma connector c ? measurement point note: fr4 test channel is bypass ed for 1-inch input trace case.
idt 89HP0504PB data sheet 19 february 8, 2011 figure 14 transmitter swing leve ls with and without de-emphasis note: v tx-diff-pkpk peak to peak voltage is twice as large as voltage diff erence between p pins and n pins of differential pairs. for example, if the p pin swings from 0.8v to 1.4v while the n pin swings from 1.4v to 0.8v, then:v tx-diff-pkpk = 2*(1.4-0.8)=1.2v. figure 15 definition of latency timing v tx-diff v tx-de-emp p n v tx-de-emp-pkpk v tx-diff-pkpk v cm v tx_emp_delay de-emphasis (db) = 20log(v tx-de-emp / v tx-diff ) rx input tx output t latency
idt 89HP0504PB data sheet 20 february 8, 2011 pin description note: unused pins can be left floating. pin name pin # description input/ output/ power 2 or 3 level power vdd 5, 8, 11, 21, 24, 27 1.2v (typ) power supply for repeater high speed channels and internal logic. each vdd pin should be connected to the vdd plane through a low inductance path, with a via located as close as possible to the landing pad of vdd pins. it is rec - ommended to have a 0.01 f or 0.1 f, x7r, size-0402 bypass capacitor from each vdd pin to ground plane. power vss center pad vss reference. vss should be connected to the ground plane through a low inductance path, with a via located as close as possible to the landing pad. power data signals a0rxn a0rxp 4 3 channel a0 receive data ports input a0txn a0txp 28 29 channel a0 transmit data ports output b0rxn b0rxp 25 26 channel b0 receive data ports input b0txn b0txp 7 6 channel b0 transmit data ports output a1rxn a1rxp 10 9 channel a1 receive data ports input a1txn a1txp 22 23 channel a1 transmit data ports output b1rxn b1rxp 19 20 channel b1 receive data ports input b1txn b1txp 13 12 channel b1 transmit data ports output channel control and status a0rxeq (channel a0) b0rxeq (channel b0) a1rxeq (channel a1) b1rxeq (channel b1) 15 17 36 33 receiver equalization. programming of channel a0 via pins is shown below. to pro - gram other channels, use pins for those channels. a0rxeq setting vss 2db open 6db (default) vdd 14db input - 3 level table 14 pin description (part 1 of 2)
idt 89HP0504PB data sheet 21 february 8, 2011 a0txsw (channel a0) b0txsw (channel b0) a1txsw (channel a1) b1txsw (channel b1) 1 32 14 18 transmitter voltage swing (pk-pk). programming of channel a0 via pins is shown below. to pro - gram other channels, use pins for those channels. a0txsw swing de-emphasis vss 0.5vdiff-pkpk 0db open 0.8vdiff-pkpk (default) -3.5db vdd 0.95vdiff-pkpk -6.5db input - 3 level other control signals pdb 35 power-down enable. pdb setting vss powerdown ic. rx terminations are in hi-z, tx is disabled vdd normal operation (internal 11k ohm mini - mum pull-up applied) input - 2 level rstb 34 receiver detection start. rstb setting vss resets channel receiver detection state machine vdd normal operation (internal 11k ohm mini - mum pull-up applied) note: the rising edge of rstb will start the receiver detec - tion. input - 2 level arxdeten brxdeten 16 31 output channel receiver detect enable input. programming of channel arxdeten via pins is shown below. to program brxdeten, use pins for that channel. arxdeten settin g vss receiver detection is disabled for a0 and a1 channels (internal 11k ohm minimum pull- down applied) vdd receiver detection is enabled for a0 and a1 channels input - 2 level chsel 30 channel transfer mode. chsel setting vss multi-cast mode open direct-connect mode (default) vdd cross-connect mode input - 3 level rsvd 2 reserved. do not connect. pin name pin # description input/ output/ power 2 or 3 level table 14 pin description (part 2 of 2)
idt 89HP0504PB data sheet 22 february 8, 2011 package pinout ? 36-qfn signal pinout table 15 lists the pin numbers and signal names for the p0504pb device. function pin function pin function pin a0rxeq 15 arxdeten 16 b1txsw 18 a0rxn 4 b0rxeq 17 brxdeten 31 a0rxp 3 b0rxn 25 chsel 30 a0txn 28 b0rxp 26 pdb 35 a0txp 29 b0txn 7 rstb 34 a0txsw 1 b0txp 6 rsvd 2 a1rxeq 36 b0txsw 32 vdd 5 a1rxn 10 b1rxeq 33 vdd 8 a1rxp 9 b1rxn 19 vdd 11 a1txn 22 b1rxp 20 vdd 21 a1txp 23 b1txn 13 vdd 24 a1txsw 14 b1txp 12 vdd 27 table 15 alphabetical pin list
idt 89HP0504PB data sheet 23 february 8, 2011 pin diagram the following figure lists the pin numbers and the signal names for the 36-qfn package. figure 16 pin diagram ? top view
idt 89HP0504PB data sheet 24 february 8, 2011 qfn package dimension
idt 89HP0504PB data sheet 25 february 8, 2011 revision history november 2, 2010: initial publication of final datasheet. february 8, 2011: removed black pack a ging options from order page.
corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: siphelp@idt.com phone: 408-284-8208 ? 26 february 8, 2011 idt 89HP0504PB data sheet disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, wh ether express or implied, including, but not limited to, the suit ability of idt?s products for any particular purpose, an impli ed warranty of merchantability, or non-infringe ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. ordering information valid combinations 89HP0504PBzbnrg / 89HP0504PBzbnrg8 36-pin green qfn package, commercial temperature 89HP0504PBzbnrgi / 89HP0504PBzbnrgi8 36-pin green qfn package, industrial temperature nn a a aa a operating voltage product device temp h product family 89 signal integrity product p repeater 1.2v +/- 5% detail legend a = alpha character n = numeric character nn chnls 04 4 channels nn speed 05 5gbps i industrial temperature (-40 c to +85 c ambient) zb revision zb n tape & range reel 8 tape & reel aaa pkg pb pcie interface, ?b? version aa protocol nrg36 36-pin qfn, green nrg revision blank commercial temperature (0c to +70c ambient)

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